Phase-lock loops (PLL) include a phase-frequency detector (PFD) that provides control signals indicative of a phase difference between a reference clock signal and a feedback clock signal such as a VCO clock of a voltage controlled oscillator (VCO). A charge pump converts a digital output of the PFD to an analog current (or signal) which is then integrated by a loop filter to generate a control voltage. The VCO provides an oscillation signal responsive to the voltage signal. However, prior to the reference clock signal becoming stabilized with the feedback clock signal, a phase-lock loop transient overshoot may exceed a clock tree bandwidth. In such a circumstance, the phase-frequency detector may not receive any feedback clock signal and thus synchronization may not occur. The phase-lock loop may not be able to recover from this condition. Another problem with transient overshoot is the power management while the phase-lock loop is acquiring the lock between the reference clock signal and the feedback clock signal. If the phase-lock loop produces a very high frequency upon starting up, then a large current may cause the power to collapse in such a way that the circuit may not be able to recover. Accordingly, it is desirable to prevent the phase-lock loop from generating a transient overshoot of its frequency while acquiring synchronization between the reference clock signal and the feedback clock signal.